There is a display device in which an image is displayed by supplying scanning signals through a plurality of gate lines and pixel signals through a plurality of source lines to a plurality of pixels provided in a display region. For such a display device, downsizing of the display device and enlargement of the display region have been required. Thus, downsizing of the transistor and circuit has been required so as to reduce the width of a peripheral region located outside the display region.
In the display region of the display device, the plurality of pixels include pixel transistors and are formed by crossing the plurality of gate lines and the plurality of source lines. Further, a gate driver for supplying scanning signals to the plurality of pixels and a source driver for supplying pixel signals to the plurality of pixels are disposed in the peripheral region of the display device.
For example, as techniques relating to the gate driver of a display device, Japanese Patent Application Laid-Open Publication No. 2012-58502 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2007-52291 (Patent Document 2) can be cited. Patent Document 1 describes a technique for applying a ground voltage as an intermediate voltage during switching between a high voltage and a low voltage in a shift register circuit of the gate driver. Patent Document 2 describes a technique in which, when a gate pulse is to be applied, a certain amount of time at an intermediate potential is secured for a period before the gate line voltage reaches a voltage at which the pixel transistor is turned off, at the time of the pulse falling that is a process in which the voltage of a gate pulse changes to the non-selective state from the selective state.